The reference design shown in this work uses embedded Linux on commercially available hardware costing $150. In order to accomplish this goal, several design considerations need to be taken into account that limit the use of high level abstractions in favor of techniques that optimize performance. For humans to be able to process and react to an image there should not be more than a 100ms delay between the time a camera captures an image and subsequently displays that image to the user. In order to achieve acceptable frame-per-second (fps) performance with low latency, it is important to understand the response time requirements that the system needs to meet. The use of resource constrained inexpensive hardware places restrictions on the design of streaming video and image processing system performance. In our experiments using Optical Flow and MeanShift Tracking, representative high-level algorithms, data show that partitioning algorithms can reduce total power by up to 25% and 30%, respectively, without impacting performance.

Compared to commercial FPGA synthesis and High Level Synthesis tools, our results show that the proposed algorithms can result in up to 60% higher utilization efficiency, increasing the sizes and/or number of frames that can be accommodated, and reduce frame buffers’ dynamic power consumption by up to approximately 70%. Based on a formalization of on-chip memory configuration options and a power model, we demonstrate how our partitioning algorithms can outperform traditional strategies. We propose methods for generating memory architectures, from both Hardware Description Languages and High Level Synthesis designs, which minimize memory usage and power consumption. In this paper, we investigate allocation of on-chip memory resources in order to minimize resource usage and power consumption, contributing to the realization of power-efficient high-level image processing fully contained on FPGAs. Since FPGAs have limited on-chip memory capabilities, efficient use of such resources is essential to meet performance, size and power constraints. Memory is the biggest limiting factor to the widespread use of FPGAs for high-level image processing, which require complete frame(s) to be stored in situ.

Tailoring design programs for computers